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Senior Verification Engineer - UVM / SystemVerilog / Python / Perl / Bash / TCL We are partnered with a Barcelona-based semiconductor company seeking mid- to senior-level Verification Engineers to join on a permanent basis, working onsite in central Barcelona. Visa sponsorship is available, and Spanish lessons are provided. MSc or PhD in a related field 4 years relevant experience Proficiency in SystemVerilog and UVM Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tool…
